10. CACHE Instructions

10.12 Hit Invalidate (D)

If the DState is not equal to 00 (Invalid) and the PA of the CACHE instruction matches the DTag from the data cache tag array, then the State bits are written to 00 (Invalid), the SCWay bit = 0, the StateMod bits = 0012 (Normal), and the DState parity = 0.

The LRU bit is left unchanged.

Parity check is enabled.

Hit CacheOps can cause cache error exceptions if they check ECC or parity bits.